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COURSE SCHEDULE ![]()
| | Introdution, performance, computer design | |||
| | Evaluating performance and cost | |||
| | ISA design principles and the VAX (CISC) | |||
| | DLX (RISC), compiler effects, ISA measurements | Hw 2 | ||
| | Basic pipelining, pipeline hazards | |||
| | Control hazards | |||
| | Multicycle operations, exceptions | |||
| | Instruction level parallelism, dynamic scheduling | |||
| | Branch prediction | |||
| | Speculation and compilers | |||
| | Multiple instruction issue, speculation | |||
| | Midterm exam (Gates B01) | |||
| | MIPS R10k pipeline | |||
| | Caches 1: design, evaluation, reducing misses | |||
| | Caches 2: reducing penalities | |||
| | Memory 1: main memory | |||
| | Memory: virtual memory, 21064 memory hierarchy | |||
| | I/O: performance, disks, buses | |||
| | I/O: memory interface, I/O benchmarks | |||
| | I/O: I/O design, file caches | |||
| | Final exam (3:30-6:30pm) |
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Last Modified: 11/01/98
by Robert Kunz (rck@leland.stanford.edu)