In class we discussed the FUPA that for floating point units there were a spectrum of ``good'' designs that satisfied AF TF = KF, where AF is the chip area used by the floating point unit, TF is the excess delay (in cycles) due to floating point latency, and KF is a constant.
Suppose we could show that a similar concept exists for cache. That is,
Ac Tc2 = Kc
where Ac is the cache area and Tc is the excess delay (in cycles) due to cache misses.
For a given fixed area A (A= Ac +AF), find an allocation of Ac and AF which minimizes T, where T= TF +Tc. Your expression will be in terms of KF, Kc, and A.
Do not attempt to reduce the solution to simple terms.