Memory, Buffers and Queues

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Table of Contents

Buffers

Maximum-Rate Buffer Design

Maximum-Rate Buffer Example

Mean-Rate Buffer Design

Mean-Rate Buffer Design

Mean-Rate Buffer Example

Cache

Cache

Target Miss Rate Trend

Target Miss Rate Trend

System Effects

Multi-Level Caches

Multi-Level Caches

Multi-Level Cache Example

Logical Inclusion

Logical Inclusion

Outline: Memory and Queuing Models

Outline: Memory and Queuing Models

Memory

Physical Memory System

Achieved vs. Offered Bandwidth

DRAM Technology (text section 6.2)

DRAM Technology (text section 6.2)

Technology and Market Trends

Technology and Market Trends

Techniques to Increase DRAM Bandwidth

Fast Page Mode (FPM)

Synchronous DRAM (SDRAM)

RAMBus DRAM (RDRAM)

RAMBus DRAM (RDRAM)

RAMBus DRAM (RDRAM)

Memory Module

Memory Module

Memory system

Processor memory model

Basic terms

Modeling and Evaluation Methodology

Modeling and Evaluation Methodology

Models for computing B(m,n); text 6.3

Strecker‰fs model

Queuing Models, text 6.4

Key Model Characteristics

Key Model Characteristics

Binomial arrivals, text 6.4.1

Poisson distribution, text 6.4.1

Queuing Properties, text 6.4.5

Pollaczek-Khinchin (P-K) Theorem

Open vs Closed queues, text 6.5

Open vs Closed queues, text 6.5

Closed Queues, text 6.5.2

_-Binomial Model

_-Binomial Example

Buffers for M/M/1, text 6.6.2

Caches and Memory

Cache Line Access Time

Write-Back Cache Example

Write-Back Cache Example

Shared Bus

Bus Model, text 6.8.9

Memory System Evaluation Summary

Memory System Evaluation Summary

Author: Mike Flynn

Email: gere@mimd.stanford.edu

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